Pritam Majumder (my cv)
Ph.D Student (Teaching Assistant)
Computer Science and Engineering
Texas A&M University
Office: 338C, Harvey R Bright Building
College Station, Texas 77843-3112
Email: pritam2309[at]tamu[dot]edu


2015-Current: Texas A&M University, Ph.D, Computer Science and Engineering (Texas, USA)

2012-2015: Indian Institute of Technology Madras (IIT Madras), MS by Research, Computer Science and Engineering (Chennai, India)

2007-2011: WBUT, BTech, Computer Science and Engineering (Kolkata, India)


I am working in Computer Architecture area and more specifically on Network on Chip (NoC) with Dr EJ Kim as a part of HPCL Lab. In NoC, multiple homogeneous or heterogeneous nodes are connected with each other through a network. Each of the nodes must contain a router. A node can be a processing node, with processing core, or a node can be a memory node, with memory controller. Other than that a node can be a I/O node also. All sorts of nodes are connected through a network, which acts as the backbone of the chip. Hence, NoC is one of the most critical shared resource in the chip. Any change in the NoC performance is reflected in the system performance also. Most importantly, NoC is easily scalable to huge number of nodes if it is designed carefully. Following are some of the major projects, on which I am currently working on or successfully completed.

In Memory Computation: Network is one of the shared resources and also the backbone for the Chip Multi Processors (CMPs). Emerging memory technologies like, Hybrid Memory Cube (HMC) opens up the opportunity for in-memory computations. That significantly reduces the response traffic. Since, for a large number of applications the memory access pattern is bursty, it needs internal as well as external memory bandwidth. (Duration: Sep 2016 - Present)

LLC Deduplication and Compression: In memory system multiple levels of caches are present. The last level cache misses are responsible for off-chip memory communication. Higher the rate of off-chip memory communication higher will be the network contention and lower will be the system performance. One of the popular ways for improving LLC hit rate is to increase the effective LLC capacity. We observe significant amount of LLC blocks contain duplicate data values and occupies unnecessary spaces in LLC. This space could be utilized to keep other unique data blocks that contains different data values, which may improve cache hit rate. Data compression is another orthogonal technique, which exploits data similarity to store data in a more concise fashion. (Duration: Feb 2016 - Mar 2017)

Approximate NoC: Power and performance are two major challenges in NoC and most of the time they come as trade-off to each other. We can improve both for some specific kind of applications, which make use of the network to a good extent and also allows some impreciseness in the value of the data transferred. For instance, video and audio applications allow some impreciseness at the output, which is beyond the human perception. NoC spends a lot of time and energy on transferring precise data, even though that is not required sometimes. (Duration: Dec 2015 - Nov 2016)

Coherence aware LLC replacement: In CMP environment coherency is one of the major concerns. When multiple threads of the same application run on different cores, they share datablocks because of inherent semantics of the program. Hence, there may exist multiple copies of the same data block in processor's private caches as well as in shared LLC. In an inclusive cache structure we should consider the sharer information before block eviction. There are several machine learning based replacement policies that can learn the program behavior and improve cache performance significantly. However, they have not considered the coherence information as part of the learning features. We implemented "Sampling Based Dead Block Prediction" and "Perceptron Based Reuse Prediction" techniques and incorporate coherence states and sharer information as learning features. We speculate that it may improve the last level cache replacement. (Duration: Jan 2017 - May 2017)

Low Power Network On Chip: The Network-On-Chip (NOC) is the future of high performance computing, whose backbone is the routers, connected through physical channels. The router energy dissipation is one of the biggest concern in NOC. Along with dynamic energy, each router consumes a huge amount of static energy as well, which suggests that a good amount of time routers remain idle. To reduce the static energy consumption by the routers, we need to study the router occupancy and network utilizations closely, so that we can minimize the router power consumption without hampering the system performance. (Duration: Aug 2015 - Dec 2015)

Energy Optimization for Data Cache Memory: Conventionally, consecutively addressed blocks are mapped onto different sets in cache. In this work, we propose a new block address mapping, Set-First Fill (SFFMap), for pipelined L1 data caches wherein consecutively addressed data blocks are mapped onto the same set. This increases the inter-block spatial locality within the cache set. In order to exploit SFFMap, we propose to store and if possible, access the most recently used set in the cache's pipeline registers. Further, selective access (SSA) and selective update (SSU) techniques are proposed for set- buffer to increase the effectiveness of SFFMap. Our experimental evaluation for in-order and out-of-order processors with an 8-way set-associative data cache shows that SFFMap, together with SSA and SSU, achieves around 27% reduction in dynamic energy and 4-5% performance improvement. The proposed techniques need minor modifications to the existing hardware, making it an adoptable design. (This work is done as a part of my masters thesis under guidance of Prof Madhu Mutyam, PACE Lab, CSE Dept, IIT Madras (Duration: July 2013 - Jan 2015)


Pritam Majumder, T.V. Kalyan, and Madhu Mutyam, SFFMap: Set-First Fill Mapping for an Energy Efficient Pipelined Data Cache 32nd IEEE International Conference on Computer Design (ICCD), October 19-22, 2014, Seoul, South Korea

Masters thesis: Energy Efficiency of Pipelined Data Caches

Rahul Boyapati, Jiayi Huang, Pritam Majumder, Ki Hwan Yum, Eun Jung Kim, APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures, The 44th International Symposium on Computer Architecture (ISCA), June 24-28, 2017, Toronto, ON, Canada

Internship(s)/ Co-Op(s)

1. Spring'15: I was an Intern/Co-op in AMD Bangalore, India. Worked as an intern in AMD India Pvt Ltd, Bangalore for 6 months on "Workload Characterization", testing and validating the results obtained from both the silicon and simulators. Carried out both qualitative and quantitative comparisons for the given workloads (SPEC CPU2000, CPU2006 and CPU-v6) across different architectural configurations. Characterized the workloads depending upon several performance parameters.

2. Fall'17: I worked in AMD Research, Austin, USA for Fall'17 semester in "Path Forward" project of Department of Energy, USA. This project targets exascale computers as future of computing. My focus was in investigating the scope for power and performance improvement in cpu front-end.

Research Assistant

I was a Research Assistant in Fall 2015, working on Low Power NoC project.

Teaching Assistant


CSCE 221: Data Structures and Algorithms, Sec:509, 510, 511 Dr Teresa Leyk, TAMU, Spring 2018

CSCE 312: Computer Organization, Sec:301, Dr Aakash Tyagi, TAMU, Summer-II 2017
CSCE 221: Data Structures and Algorithms, Sec:202, Dr Teresa Leyk, TAMU, Summer-II 2017
CSCE 312: Computer Organization (Section: 504, Dr Yum, Tuesday 11:10am - 12:50pm), TAMU, Spring 2017 Lab Page
CSCE 312: Computer Organization (Section: 502, Dr Jimenez, Tuesday 3:10pm - 5:00pm), TAMU, Spring 2017 Course Page [Lab Quiz]
CSCE 312: Computer Organization, TAMU, Fall 2016
CSCE 350: Computer Architecture & Design, TAMU, Spring 2016 [Main Course Page] [Lab Page]
CSCE 111: CPSC Comcepts & Program, TAMU, Spring 2016
CS 1100: Computational Engineering, IIT Madras, India, Fall 2014
CS 6560: Parallel Computer Architecture, IIT Madras, India, Spring 2014
CS 4100: Computer System Design, IIT Madras, India, Fall 2013
CS 1100: Computational Engineering, IIT Madras, India, Spring 2013
CS 4100: Computer System Design, IIT Madras, India, Fall 2012
CS 1100: Computational Engineering, IIT Madras, India, Spring 2012

Personal Interests

  • Photography: I like photography. Human, nature, rural, urban almost any kind.
  • Painting: I like to do oil color on canvus. I like also scetching using pencil and charcoal.
  • Bike: I love riding my bike.
  • Badminton: I like to play badminton. I also like to workout in Gym.
  • Cooking and eating: I love to cook, if I get time. I always love to eat different cuisines in different places.
  • Keyboard: I like to play keyboard in leisure (difficult to find).
  • Reading story books and listening to music.
  • Watching good movies. I watch all sorts of movies, starting from romance to action/trillers. I don't like horror movies at all.